{"id":873,"date":"2024-07-14T03:36:50","date_gmt":"2024-07-14T03:36:50","guid":{"rendered":"https:\/\/drjuliovazqueztechdesign.com\/?page_id=873"},"modified":"2024-08-21T15:30:29","modified_gmt":"2024-08-21T15:30:29","slug":"estudios","status":"publish","type":"page","link":"https:\/\/drjuliovazqueztechdesign.com\/en\/estudios\/","title":{"rendered":"Education"},"content":{"rendered":"<div class=\"wp-block-stackable-columns alignwide stk-block-columns stk-has-top-separator stk-has-bottom-separator stk-block stk-88ea420 stk-block-background\" data-block-id=\"88ea420\"><div class=\"stk-separator stk-separator__top\"><div class=\"stk-separator__wrapper\"><svg xmlns=\"http:\/\/www.w3.org\/2000\/svg\" viewbox=\"0 0 1600 200\" class=\"stk-separator__layer-1\" preserveaspectratio=\"none\" aria-hidden=\"true\"><path class=\"wave-1_svg__st2\" d=\"M1341.4 48.9c-182.4 0-254.2 80.4-429.4 80.4-117.8 0-209.7-67.5-393.5-67.5-142.2 0-212.6 38.8-324.6 38.8S-10 64.7-10 64.7V210h1620V102c-110.6-40.2-181-53.1-268.6-53.1z\"><\/path><\/svg><\/div><\/div><div class=\"stk-row stk-inner-blocks stk-block-content stk-content-align stk-88ea420-column alignwide\">\n<div class=\"wp-block-stackable-column stk-block-column stk-column stk-block stk-0b3a4f4\" data-v=\"4\" data-block-id=\"0b3a4f4\"><div class=\"stk-column-wrapper stk-block-column__content stk-container stk-0b3a4f4-container stk--no-background stk--no-padding\"><div class=\"stk-block-content stk-inner-blocks stk-0b3a4f4-inner-blocks\">\n<div class=\"wp-block-stackable-heading stk-block-heading stk-block-heading--v2 stk-block stk-31e4d42\" id=\"doctorado-br-diseno-de-circuitos-integrados-vlsi\" data-block-id=\"31e4d42\"><style>.stk-31e4d42{margin-bottom:50px !important}.stk-31e4d42 .stk-block-heading__text{color:var(--theme-palette-color-3,#3A4F66) !important}<\/style><h2 class=\"stk-block-heading__text has-text-color has-text-align-center\">Ph. D. Degree<br>Integrated Circuit, VLSI Design<\/h2><\/div>\n\n\n\n<div class=\"wp-block-stackable-columns stk-block-columns stk-block stk-8193d5d\" data-block-id=\"8193d5d\"><div class=\"stk-row stk-inner-blocks stk-block-content stk-content-align stk-8193d5d-column\">\n<div class=\"wp-block-stackable-column stk-block-column stk-column stk-block stk-e23c053\" data-v=\"4\" data-block-id=\"e23c053\"><div class=\"stk-column-wrapper stk-block-column__content stk-container stk-e23c053-container stk--no-background stk--no-padding\"><div class=\"stk-block-content stk-inner-blocks stk-e23c053-inner-blocks\">\n<p class=\"has-text-align-center\" style=\"font-size:clamp(16.293px, 1.018rem + ((1vw - 3.2px) * 0.68), 25px);\">Thesis: <span style=\"color: #0693e3;\" class=\"stk-highlight\"><strong>Aging Robust Monitoring and techniques to improve Performance on Digital Systems.<\/strong><\/span><\/p>\n\n\n\n<div class=\"wp-block-stackable-text stk-block-text stk-block stk-64c440a\" data-block-id=\"64c440a\"><style>.stk-64c440a{margin-bottom:0px !important}.stk-64c440a .stk-block-text__text{font-size:17px !important}@media screen and (max-width:1023px){.stk-64c440a .stk-block-text__text{font-size:17px !important}}<\/style><p class=\"stk-block-text__text has-text-align-justify\">In order to ensure reliable operation in advanced technologies, aging monitoring must be developed within the chip using built-in aging sensors. The main methods to develop such aging monitoring are classified into two groups: a) Error Prediction and b) Error Correction. In this thesis, various methodologies and schemes will be proposed to achieve robust aging monitoring for error prediction and correction in nanometric digital integrated circuits. <\/p><\/div>\n\n\n\n<div class=\"wp-block-stackable-image stk-block-image stk-block stk-68dbe03\" data-block-id=\"68dbe03\"><style>.stk-68dbe03{margin-bottom:0px !important}.stk-68dbe03 .stk-img-wrapper{width:50% !important}<\/style><figure><span class=\"stk-img-wrapper stk-image--shape-stretch\"><img loading=\"lazy\" decoding=\"async\" class=\"stk-img wp-image-1221\" src=\"https:\/\/drjuliovazqueztechdesign.com\/wp-content\/uploads\/2024\/07\/Presentacion-Tesis-doctoral2.png\" width=\"2125\" height=\"1582\" srcset=\"https:\/\/drjuliovazqueztechdesign.com\/wp-content\/uploads\/2024\/07\/Presentacion-Tesis-doctoral2.png 2125w, https:\/\/drjuliovazqueztechdesign.com\/wp-content\/uploads\/2024\/07\/Presentacion-Tesis-doctoral2-300x223.png 300w, https:\/\/drjuliovazqueztechdesign.com\/wp-content\/uploads\/2024\/07\/Presentacion-Tesis-doctoral2-1024x762.png 1024w, https:\/\/drjuliovazqueztechdesign.com\/wp-content\/uploads\/2024\/07\/Presentacion-Tesis-doctoral2-768x572.png 768w, https:\/\/drjuliovazqueztechdesign.com\/wp-content\/uploads\/2024\/07\/Presentacion-Tesis-doctoral2-1536x1144.png 1536w, https:\/\/drjuliovazqueztechdesign.com\/wp-content\/uploads\/2024\/07\/Presentacion-Tesis-doctoral2-2048x1525.png 2048w\" sizes=\"auto, (max-width: 2125px) 100vw, 2125px\" \/><\/span><\/figure><\/div>\n\n\n\n<div class=\"wp-block-stackable-text stk-block-text stk-block stk-4b44bae\" data-block-id=\"4b44bae\"><style>.stk-4b44bae .stk-block-text__text{font-size:17px !important}@media screen and (max-width:1023px){.stk-4b44bae .stk-block-text__text{font-size:17px !important}}<\/style><p class=\"stk-block-text__text has-text-align-justify\">As technological scaling has progressed, aging effects such as Negative Bias Temperature Instability (NBTI) have become of utmost importance in nanometric CMOS technologies. On the other hand, the impact of parametric variations has further exacerbated these effects. Process, Voltage, Temperature, and Aging variations (PVTA) have a strong impact on the reliability and performance of integrated circuits in operation. NBTI-induced aging causes performance degradation as the operation time increases. The rate of this degradation depends on: a) the operational conditions experienced by the circuits, such as Voltage, Temperature, and the electrical stress time of MOS transistors, and b) the static technological parameters defined in the fabrication process. <\/p><\/div>\n<\/div><\/div><\/div>\n\n\n\n<div class=\"wp-block-stackable-column stk-block-column stk-column stk-block stk-64feea0\" data-v=\"4\" data-block-id=\"64feea0\"><div class=\"stk-column-wrapper stk-block-column__content stk-container stk-64feea0-container stk--no-background stk--no-padding\"><div class=\"stk-block-content stk-inner-blocks stk-64feea0-inner-blocks\">\n<div class=\"wp-block-stackable-image stk-block-image stk-block stk-6dca7c7\" data-block-id=\"6dca7c7\"><style>.stk-6dca7c7 .stk-img-wrapper{width:100% !important}<\/style><figure><span class=\"stk-img-wrapper stk-image--shape-stretch\"><img loading=\"lazy\" decoding=\"async\" class=\"stk-img wp-image-1172\" src=\"https:\/\/drjuliovazqueztechdesign.com\/wp-content\/uploads\/2024\/07\/Certificado-Doctorado.jpeg\" width=\"581\" height=\"739\" srcset=\"https:\/\/drjuliovazqueztechdesign.com\/wp-content\/uploads\/2024\/07\/Certificado-Doctorado.jpeg 581w, https:\/\/drjuliovazqueztechdesign.com\/wp-content\/uploads\/2024\/07\/Certificado-Doctorado-236x300.jpeg 236w\" sizes=\"auto, (max-width: 581px) 100vw, 581px\" \/><\/span><\/figure><\/div>\n<\/div><\/div><\/div>\n<\/div><\/div>\n<\/div><\/div><\/div>\n<\/div><div class=\"stk-separator stk-separator__bottom\"><div class=\"stk-separator__wrapper\"><svg xmlns=\"http:\/\/www.w3.org\/2000\/svg\" viewbox=\"0 0 1600 200\" class=\"stk-separator__layer-1\" preserveaspectratio=\"none\" aria-hidden=\"true\"><path class=\"wave-1_svg__st2\" d=\"M1341.4 48.9c-182.4 0-254.2 80.4-429.4 80.4-117.8 0-209.7-67.5-393.5-67.5-142.2 0-212.6 38.8-324.6 38.8S-10 64.7-10 64.7V210h1620V102c-110.6-40.2-181-53.1-268.6-53.1z\"><\/path><\/svg><\/div><\/div><\/div>\n\n\n\n<div class=\"wp-block-stackable-columns alignwide stk-block-columns stk-has-top-separator stk-has-bottom-separator stk-block stk-2bb2c6b stk-block-background\" data-block-id=\"2bb2c6b\"><div class=\"stk-separator stk-separator__top\"><div class=\"stk-separator__wrapper\"><svg xmlns=\"http:\/\/www.w3.org\/2000\/svg\" viewbox=\"0 0 1600 200\" class=\"stk-separator__layer-1\" preserveaspectratio=\"none\" aria-hidden=\"true\"><path class=\"wave-1_svg__st2\" d=\"M1341.4 48.9c-182.4 0-254.2 80.4-429.4 80.4-117.8 0-209.7-67.5-393.5-67.5-142.2 0-212.6 38.8-324.6 38.8S-10 64.7-10 64.7V210h1620V102c-110.6-40.2-181-53.1-268.6-53.1z\"><\/path><\/svg><\/div><\/div><div class=\"stk-row stk-inner-blocks stk-block-content stk-content-align stk-2bb2c6b-column alignwide\">\n<div class=\"wp-block-stackable-column stk-block-column stk-column stk-block stk-2c48a26\" data-v=\"4\" data-block-id=\"2c48a26\"><div class=\"stk-column-wrapper stk-block-column__content stk-container stk-2c48a26-container stk--no-background stk--no-padding\"><div class=\"stk-block-content stk-inner-blocks stk-2c48a26-inner-blocks\">\n<div class=\"wp-block-stackable-heading stk-block-heading stk-block-heading--v2 stk-block stk-18aec97\" id=\"maestria-br-diseno-de-circuitos-integrados-vlsi\" data-block-id=\"18aec97\"><style>.stk-18aec97{margin-bottom:50px !important}.stk-18aec97 .stk-block-heading__text{color:var(--theme-palette-color-3,#3A4F66) !important}<\/style><h2 class=\"stk-block-heading__text has-text-color has-text-align-center\">M.Sc. Degree<br>Integrated Circuit, VLSI Design<\/h2><\/div>\n\n\n\n<div class=\"wp-block-stackable-columns stk-block-columns stk-block stk-c405444\" data-block-id=\"c405444\"><div class=\"stk-row stk-inner-blocks stk-block-content stk-content-align stk-c405444-column\">\n<div class=\"wp-block-stackable-column stk-block-column stk-column stk-block stk-2474582\" data-v=\"4\" data-block-id=\"2474582\"><div class=\"stk-column-wrapper stk-block-column__content stk-container stk-2474582-container stk--no-background stk--no-padding\"><div class=\"stk-block-content stk-inner-blocks stk-2474582-inner-blocks\">\n<p class=\"has-text-align-center\" style=\"font-size:clamp(16.293px, 1.018rem + ((1vw - 3.2px) * 0.68), 25px);\">Thesis: <span style=\"color: #0693e3;\" class=\"stk-highlight\"><strong>Analysis and simulation of Stuck-Open Faults in Digital Circuits based on FinFET technologies<\/strong><\/span><\/p>\n\n\n\n<div class=\"wp-block-stackable-text stk-block-text stk-block stk-4b7e95f\" data-block-id=\"4b7e95f\"><style>.stk-4b7e95f .stk-block-text__text{font-size:17px !important}@media screen and (max-width:1023px){.stk-4b7e95f .stk-block-text__text{font-size:17px !important}}<\/style><p class=\"stk-block-text__text has-text-align-justify\">VLSI integrated circuit design has been based on the MOSFET device for the past three decades. However, scaling down the MOSFET to the nanometer regime presents some undesirable effects that degrade the performance of this device. One option to continue technological scaling beyond 32nm is the use of new structures, such as double-gate transistors (DGMOSFETs), which find the most suitable way to be fabricated in the FinFET. The International Technology Roadmap for Semiconductors (ITRS) recognizes the importance of these devices in future technologies. <\/p><\/div>\n\n\n\n<div class=\"wp-block-stackable-image stk-block-image stk-block stk-000208e\" data-block-id=\"000208e\"><style>.stk-000208e{margin-bottom:0px !important}.stk-000208e .stk-img-wrapper{width:50% !important}<\/style><figure><span class=\"stk-img-wrapper stk-image--shape-stretch\"><img loading=\"lazy\" decoding=\"async\" class=\"stk-img wp-image-1178\" src=\"https:\/\/drjuliovazqueztechdesign.com\/wp-content\/uploads\/2024\/07\/Imagen-finFET.jpeg\" width=\"633\" height=\"522\" srcset=\"https:\/\/drjuliovazqueztechdesign.com\/wp-content\/uploads\/2024\/07\/Imagen-finFET.jpeg 633w, https:\/\/drjuliovazqueztechdesign.com\/wp-content\/uploads\/2024\/07\/Imagen-finFET-300x247.jpeg 300w\" sizes=\"auto, (max-width: 633px) 100vw, 633px\" \/><\/span><\/figure><\/div>\n\n\n\n<div class=\"wp-block-stackable-text stk-block-text stk-block stk-d4bfe30\" data-block-id=\"d4bfe30\"><style>.stk-d4bfe30 .stk-block-text__text{font-size:17px !important}@media screen and (max-width:1023px){.stk-d4bfe30 .stk-block-text__text{font-size:17px !important}}<\/style><p class=\"stk-block-text__text has-text-align-justify\">The FinFET belongs to the family of devices based on Silicon-on-Insulator technologies. It is a fin-shaped device, which is surrounded by a gate electrode forming two properly aligned channels on the vertical walls of the fin. Stuck-open faults have traditionally been recognized as difficult to detect in technologies mainly because they require a sequence of vectors for their detection. As future technologies increase the density of devices, the number of metals, and the number of vias, there will be a higher probability of having stuck-open faults. This work focuses on the study of stuck-open faults in static CMOS gates based on FinFET technologies. Furthermore, this work aims to determine how leakage currents in FinFETs affect the behavior of digital gates under test.<\/p><\/div>\n<\/div><\/div><\/div>\n\n\n\n<div class=\"wp-block-stackable-column stk-block-column stk-column stk-block stk-40bc6f7\" data-v=\"4\" data-block-id=\"40bc6f7\"><div class=\"stk-column-wrapper stk-block-column__content stk-container stk-40bc6f7-container stk--no-background stk--no-padding\"><div class=\"stk-block-content stk-inner-blocks stk-40bc6f7-inner-blocks\">\n<div class=\"wp-block-stackable-image stk-block-image stk-block stk-e55d587\" data-block-id=\"e55d587\"><style>.stk-e55d587 .stk-img-wrapper{width:100% !important}<\/style><figure><span class=\"stk-img-wrapper stk-image--shape-stretch\"><img loading=\"lazy\" decoding=\"async\" class=\"stk-img wp-image-1174\" src=\"https:\/\/drjuliovazqueztechdesign.com\/wp-content\/uploads\/2024\/07\/Certificado-Maestria.jpeg\" width=\"581\" height=\"734\" srcset=\"https:\/\/drjuliovazqueztechdesign.com\/wp-content\/uploads\/2024\/07\/Certificado-Maestria.jpeg 581w, https:\/\/drjuliovazqueztechdesign.com\/wp-content\/uploads\/2024\/07\/Certificado-Maestria-237x300.jpeg 237w\" sizes=\"auto, (max-width: 581px) 100vw, 581px\" \/><\/span><\/figure><\/div>\n<\/div><\/div><\/div>\n<\/div><\/div>\n<\/div><\/div><\/div>\n<\/div><div class=\"stk-separator stk-separator__bottom\"><div class=\"stk-separator__wrapper\"><svg xmlns=\"http:\/\/www.w3.org\/2000\/svg\" viewbox=\"0 0 1600 200\" class=\"stk-separator__layer-1\" preserveaspectratio=\"none\" aria-hidden=\"true\"><path class=\"wave-1_svg__st2\" d=\"M1341.4 48.9c-182.4 0-254.2 80.4-429.4 80.4-117.8 0-209.7-67.5-393.5-67.5-142.2 0-212.6 38.8-324.6 38.8S-10 64.7-10 64.7V210h1620V102c-110.6-40.2-181-53.1-268.6-53.1z\"><\/path><\/svg><\/div><\/div><\/div>\n\n\n\n<div class=\"wp-block-stackable-columns alignwide stk-block-columns stk-has-top-separator stk-has-bottom-separator stk-block stk-dc14545 stk-block-background\" data-block-id=\"dc14545\"><div class=\"stk-separator stk-separator__top\"><div class=\"stk-separator__wrapper\"><svg xmlns=\"http:\/\/www.w3.org\/2000\/svg\" viewbox=\"0 0 1600 200\" class=\"stk-separator__layer-1\" preserveaspectratio=\"none\" aria-hidden=\"true\"><path class=\"wave-1_svg__st2\" d=\"M1341.4 48.9c-182.4 0-254.2 80.4-429.4 80.4-117.8 0-209.7-67.5-393.5-67.5-142.2 0-212.6 38.8-324.6 38.8S-10 64.7-10 64.7V210h1620V102c-110.6-40.2-181-53.1-268.6-53.1z\"><\/path><\/svg><\/div><\/div><div class=\"stk-row stk-inner-blocks stk-block-content stk-content-align stk-dc14545-column alignwide\">\n<div class=\"wp-block-stackable-column stk-block-column stk-column stk-block stk-615ef2e\" data-v=\"4\" data-block-id=\"615ef2e\"><div class=\"stk-column-wrapper stk-block-column__content stk-container stk-615ef2e-container stk--no-background stk--no-padding\"><div class=\"stk-block-content stk-inner-blocks stk-615ef2e-inner-blocks\">\n<div class=\"wp-block-stackable-heading stk-block-heading stk-block-heading--v2 stk-block stk-4461c46\" id=\"ingenieria-en-electronica\" data-block-id=\"4461c46\"><style>.stk-4461c46{margin-bottom:50px !important}.stk-4461c46 .stk-block-heading__text{color:var(--theme-palette-color-3,#3A4F66) !important}<\/style><h2 class=\"stk-block-heading__text has-text-color has-text-align-center\">Electronic Engineering<\/h2><\/div>\n\n\n\n<div class=\"wp-block-stackable-columns stk-block-columns stk-block stk-ec41cc6\" data-block-id=\"ec41cc6\"><div class=\"stk-row stk-inner-blocks stk-block-content stk-content-align stk-ec41cc6-column\">\n<div class=\"wp-block-stackable-column stk-block-column stk-column stk-block stk-ca97b4e\" data-v=\"4\" data-block-id=\"ca97b4e\"><div class=\"stk-column-wrapper stk-block-column__content stk-container stk-ca97b4e-container stk--no-background stk--no-padding\"><div class=\"stk-block-content stk-inner-blocks stk-ca97b4e-inner-blocks\">\n<div class=\"wp-block-stackable-text stk-block-text stk-block stk-48bf312\" data-block-id=\"48bf312\"><style>.stk-48bf312 .stk-block-text__text{font-size:18px !important}@media screen and (max-width:1023px){.stk-48bf312 .stk-block-text__text{font-size:18px !important}}<\/style><p class=\"stk-block-text__text has-text-align-justify\">The engineering program was completed at the Instituto Tecnol\u00f3gico de Puebla. The engineering degree was automatically awarded for achieving an average grade of 90\/100 in the program's courses. Some of the most important courses that were completed in this engineering program are:<br><br>            a) Analog Electronic Systems<br>            b) Digital Electronic Systems<br>            c) Microcontrollers<br>            d) Control Systems<br>            e) Instrumentation<br>            f) PLCs<br>            g) Robotics<\/p><\/div>\n<\/div><\/div><\/div>\n\n\n\n<div class=\"wp-block-stackable-column stk-block-column stk-column stk-block stk-6515489\" data-v=\"4\" data-block-id=\"6515489\"><div class=\"stk-column-wrapper stk-block-column__content stk-container stk-6515489-container stk--no-background stk--no-padding\"><div class=\"stk-block-content stk-inner-blocks stk-6515489-inner-blocks\">\n<div class=\"wp-block-stackable-image stk-block-image stk-block stk-a5f4133\" data-block-id=\"a5f4133\"><style>.stk-a5f4133 .stk-img-wrapper{width:100% !important}<\/style><figure><span class=\"stk-img-wrapper stk-image--shape-stretch\"><img loading=\"lazy\" decoding=\"async\" class=\"stk-img wp-image-1176\" src=\"https:\/\/drjuliovazqueztechdesign.com\/wp-content\/uploads\/2024\/07\/Reconocimiento-Ingenieria.jpeg\" width=\"931\" height=\"708\" srcset=\"https:\/\/drjuliovazqueztechdesign.com\/wp-content\/uploads\/2024\/07\/Reconocimiento-Ingenieria.jpeg 931w, https:\/\/drjuliovazqueztechdesign.com\/wp-content\/uploads\/2024\/07\/Reconocimiento-Ingenieria-300x228.jpeg 300w, https:\/\/drjuliovazqueztechdesign.com\/wp-content\/uploads\/2024\/07\/Reconocimiento-Ingenieria-768x584.jpeg 768w\" sizes=\"auto, (max-width: 931px) 100vw, 931px\" \/><\/span><\/figure><\/div>\n<\/div><\/div><\/div>\n<\/div><\/div>\n<\/div><\/div><\/div>\n<\/div><div class=\"stk-separator stk-separator__bottom\"><div class=\"stk-separator__wrapper\"><svg xmlns=\"http:\/\/www.w3.org\/2000\/svg\" viewbox=\"0 0 1600 200\" class=\"stk-separator__layer-1\" preserveaspectratio=\"none\" aria-hidden=\"true\"><path class=\"wave-1_svg__st2\" d=\"M1341.4 48.9c-182.4 0-254.2 80.4-429.4 80.4-117.8 0-209.7-67.5-393.5-67.5-142.2 0-212.6 38.8-324.6 38.8S-10 64.7-10 64.7V210h1620V102c-110.6-40.2-181-53.1-268.6-53.1z\"><\/path><\/svg><\/div><\/div><\/div>","protected":false},"excerpt":{"rendered":"<p>DOCTORADODise\u00f1o de Circuitos Integrados VLSI Tesis: Monitoreo Robusto del Envejecimiento y t\u00e9cnicas para mejorar el Rendimiento en Sistemas Digitales. Para poder garantizar la operaci\u00f3n confiable en tecnolog\u00edas avanzadas un monitoreo del envejecimiento debe ser desarrollado dentro del chip usando sensores inter-construidos de envejecimiento. Las principales maneras para desarrollar dicho monitoreo del envejecimiento son clasificados en [&hellip;]<\/p>","protected":false},"author":1,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"om_disable_all_campaigns":false,"_uag_custom_page_level_css":"","_monsterinsights_skip_tracking":false,"_monsterinsights_sitenote_active":false,"_monsterinsights_sitenote_note":"","_monsterinsights_sitenote_category":0,"_uf_show_specific_survey":0,"_uf_disable_surveys":false,"footnotes":""},"class_list":["post-873","page","type-page","status-publish","hentry"],"blocksy_meta":{"has_hero_section":"disabled","styles_descriptor":{"styles":{"desktop":"","tablet":"","mobile":""},"google_fonts":[],"version":6}},"aioseo_notices":[],"uagb_featured_image_src":{"full":false,"thumbnail":false,"medium":false,"medium_large":false,"large":false,"1536x1536":false,"2048x2048":false,"trp-custom-language-flag":false},"uagb_author_info":{"display_name":"drjuliovazqueztechdesign.com","author_link":"https:\/\/drjuliovazqueztechdesign.com\/en\/author\/drjuliovazqueztechdesign-com\/"},"uagb_comment_info":0,"uagb_excerpt":"DOCTORADODise\u00f1o de Circuitos Integrados VLSI Tesis: Monitoreo Robusto del Envejecimiento y t\u00e9cnicas para mejorar el Rendimiento en Sistemas Digitales. Para poder garantizar la operaci\u00f3n confiable en tecnolog\u00edas avanzadas un monitoreo del envejecimiento debe ser desarrollado dentro del chip usando sensores inter-construidos de envejecimiento. Las principales maneras para desarrollar dicho monitoreo del envejecimiento son clasificados en&hellip;","_links":{"self":[{"href":"https:\/\/drjuliovazqueztechdesign.com\/en\/wp-json\/wp\/v2\/pages\/873","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/drjuliovazqueztechdesign.com\/en\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/drjuliovazqueztechdesign.com\/en\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/drjuliovazqueztechdesign.com\/en\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/drjuliovazqueztechdesign.com\/en\/wp-json\/wp\/v2\/comments?post=873"}],"version-history":[{"count":65,"href":"https:\/\/drjuliovazqueztechdesign.com\/en\/wp-json\/wp\/v2\/pages\/873\/revisions"}],"predecessor-version":[{"id":1320,"href":"https:\/\/drjuliovazqueztechdesign.com\/en\/wp-json\/wp\/v2\/pages\/873\/revisions\/1320"}],"wp:attachment":[{"href":"https:\/\/drjuliovazqueztechdesign.com\/en\/wp-json\/wp\/v2\/media?parent=873"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}